The MC68HC908AS60/AZ60 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCU). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
This part is designed to emulate the M68HC08ASxx automotive family.
NOTE: The MC68HC908AS60 offers extra features which are not available on
the MC68HC08AS20 and MC68HC908AS32 devices. It is the user's
responsibility to ensure compatibility between the features used on the
MC68HC908AS60 and those which are available on the device which
will ultimately be used in the application.


Features of the MC68HC908AS60 include:
* High-performance M68HC08 architecture
* Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
* 8.4-MHz internal bus frequency
* 60 Kbytes of FLASH electrically erasable read-only memory (FLASH)
* FLASH data security(1)
* 1 Kbyte of on-chip electrically erasable programmable read-only
	memory (EEPROM) with security option
* 2 Kbytes of on-chip random-access memory (RAM)
* Clock generator module (CGM)
* Serial peripheral interface module (SPI)
* Serial communications interface module (SCI)
* 8-bit, 15-channel analog-to-digital converter (ADC-15)
* 16-bit, 6-channel timer interface module (TIMA-6)
* Modulo timer (TIM)
* SAE J1850 byte data link controller digital module (BDLC-D)
* System protection features:
	- Computer operating properly (COP) with optional reset
	- Low-voltage detection with optional reset
	- Illegal opcode detection with optional reset
	- Illegal address detection with optional reset
* Low-power design with stop and wait modes
* Master reset pin and power-on reset

Features of the CPU08 include:
* Enhanced HC05 programming model
* Extensive loop control functions
* 16 addressing modes (eight more than the M68HC05)
* 16-bit index register and stack pointer
* Memory-to-memory data transfers
* Fast 8 — 8 multiply instruction
* Fast 16/8 divide instruction
* Binary-coded decimal (BCD) instructions
* Optimization for controller applications
* C language support

Default FLASH state - 00


The 512 bytes of EEPROM are divided into four 128-byte blocks. Each
of these blocks can be separately protected by EEBPx bit. Any attempt
to program or erase memory locations within the protected block will not
allow the program/erase voltage to be applied to the array. Table 1
shows the address ranges within the blocks.
If EEBPx bit is set, that corresponding address block is protected. These
bits are effective after a reset or a read to EENVR1 register. The block
protect configuration can be modified by erasing/programming the
corresponding bits in the EENVR1 register and then reading the
EENVR1 register.
Block Number (EEBPx) Address Range
EEBP0 $0800-$087F
EEBP1 $0880-$08FF
EEBP2 $0900-$097F
EEBP3 $0980-$09FF

EENVR2 register.
Block Number (EEBPx) Address Range
EEBP0 $0600-$067F
EEBP1 $0680-$06FF
EEBP2 $0700-$077F
EEBP3 $0780-$07FF

EEPRTCT - EEPROM Protection
This ONE-TIME programmable bit can be used to protect 16 bytes
$8F0-$8FF from being erased or programmed.
1 = EEPROM protection disabled
0 = EEPROM protection enabled

The new configuration will take affect after a system reset.

EENVR1,EENVR2 default state: 10000 (bin)
